Paper Contents
Abstract
In the world of digital circuits, full adders are the basic building blocks that allow arithmetic operations to be performed. They play a vital role in the design of arithmetic logic units (ALUs) and digital signal processors (DSPs). As the demand for low-power and high-speed electronic devices continues to escalate, it has become necessary to optimize full adder designs to enhance overall system efficiency. This paper describes a new low-power full adder circuit using the logical effort method, which is a systematic approach providing an effective framework to make accurate delay estimations for CMOS circuits.The proposed design has been implemented using Cadence Virtuoso software and GPDK 45nm technology in order to maintain compatibility with the modern semiconductor fabrication processes. The design process includes key strategies such as transistor resizing based on logical effort calculations, which are used to minimize delay while controlling power consumption. A detailed comparison is made against three established low-power full adder circuits, focusing on critical performance metrics, including average power consumption, delay of sum and carry outputs, power delay product (PDP), and transistor count.The experimental results reveal that the proposed design significantly outperforms the existing designs, achieving a reduction in average power consumption by 35%, and improvements in delay for sum and carry outputs by 27% and 5%, respectively. Notably, the proposed full adder circuit utilizes fewer transistors, totaling 14, compared to 16 and 20 in the other designs, thereby optimizing area efficiency as well.Varying conditions of fan-out: Further, the study brings insights about how the circuit will vary under changing conditions for the fan-out. By finding out how the performances alter based on changing power and operational speeds, the investigation presents trade-offs between reducing the consumption of power by means of efficient circuit operational speeds and maintaining operational performance without high power consumption in new applications. The results are a contribution to low-power circuit design research and, hence, pave the way for further advancement in energy-efficient digital systems.
Copyright
Copyright © 2024 VANAPARTHI.SURYA VAMSI. This is an open access article distributed under the Creative Commons Attribution License.
