Paper Contents
Abstract
Finite Impulse Response (FIR) filters are essential components indigital signal processing (DSP) applications, enabling precisefrequency domain filtering for audio processing, communicationsystems, and image enhancement. However, the computationalcomplexity of multiplication operations in FIR filters posessignificant challenges in achieving high-speed and power-efficientperformance. This work presents an optimized FIR filterarchitecture that integrates a Hybrid Vedic-Booth Multiplier(HVBM) to enhance computational efficiency, minimize powerconsumption, and reduce hardware complexity. The HVBMcombines Booth Encoding with Vedic Multiplication, efficientlyhandling signed operations while reducing the number of partialproducts. Vedic Multiplication partitions computations intosmaller 44 blocks, enabling parallel processing and minimizingpropagation delay, whereas Booth Encoding optimizes signhandling to improve computational speed. Experimental resultsdemonstrate that the proposed FIR filter achieves superiorperformance, lower latency, and reduced power consumption,making it an ideal solution for high-throughput DSPapplications, embedded systems, and VLSI implementations. Byleveraging the advantages of Vedic mathematics and BoothEncoding, this work introduces a scalable and power-efficientapproach for next-generation real-time signal processing.
Copyright
Copyright © 2025 S Parthibhan . This is an open access article distributed under the Creative Commons Attribution License.
