Recent Papers

ABSTRACT: Many applications, including health-monitoring and biometric data based recognition system, need short-term data security. To design short-term security based applications, there is an essential need of high-performance, low cost and area-efficient VLSI implementation of lightweight ciphers. Data Encryption Standard (DES) is well-suited for the implementation of low-cost lightweight cryptography applications. In this paper, we propose an efficient VLSI architecture for DES algorithm based encryptiondecryption engine. Depending upon the encryptiondecryption needs, the same set of architecture performs both encryption and decryption operations. Design of area efficient and less delay utilization is a major concern for the VLSI (Very Large Scale Integration) circuit designer. This paper presents an efficient high-speed VLSI-Architecture for Data Encryption Standard by using a Carry Select Parallel Prefix Adder (CSPPA). This results show that the suggested design has low delay and area when compared with other available designs.

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