Paper Contents
Abstract
SDRAM(synchronous dynamic RAM) memory is used in many applications like smart phones, laptops because of its reduced area, high speed, configurable and less latency and high performance and also it provides double data rate. It is important to maintain the memory refresh, read, write signals and initialize functions to implement the SDRAM memory by connecting proper signals. For this purpose the controller is designed which controls the SDRAM memory by predefined set of command signals. In this paper the optimized controller is designed and implemented on FPGA. And also the design has been focused on both read and writes operation at the same time to maintain the configurable latency.
Copyright
Copyright © 2023 Maddala Lakshmi Gayathri, B. Sarada. This is an open access article distributed under the Creative Commons Attribution License.
