Paper Contents
Abstract
In the real time of deep submicron circuits, low power consumption, compact chip size, and efficient performance are essential parameters. Striking a balance between these factors, particularly power reduction and high speed, presents a critical challenge. The emerging alternative ONOFIC technique demonstrates promise in addressing this challenge, offering significant power savings in the design of CMOS logic circuits. In this work, we propose a 4-bit excess-3 to BCD code converter utilizing this alternative ONOFIC approach and compare its performance against existing techniques like ONOFIC and stack ONOFIC.
Copyright
Copyright © 2024 Behara Sai Charan. This is an open access article distributed under the Creative Commons Attribution License.
Paper ID:
IJPREMS40800023522
ISSN:
2321-9653
Publisher:
ijprems