Paper Contents
Abstract
In the pursuit of energy-efficient electronics, power gating has emerged as a pivotal technique in the design of low power VLSI circuits. This paper presents a comprehensive performance analysis of power gating implementations in Binary Coded Decimal (BCD) adders, which are critical components in digital systems for arithmetic operations. We examine the trade-offs between power savings and potential performance penalties associated with power gating. Through a combination of simulation and analytical methods, we evaluate the effectiveness of various power gating schemes in reducing static and dynamic power dissipation. Our findings reveal the nuanced impacts of power gating on the overall performance and energy consumption of BCD adders in VLSI circuits, offering insights into design optimizations that can lead to more sustainable electronic devices. The study also highlights the challenges faced in the practical application of power gating, providing a pathway for future research in this area.
Copyright
Copyright © 2023 Thirunahari Srimannarayana Murthy. This is an open access article distributed under the Creative Commons Attribution License.
