Paper Contents
Abstract
This paper details the design, implementation, and verification of four fundamental 4-bit shift registers configuration Serial-In Serial-Out (SISO), Serial-In Parallel-Out (SIPO), Parallel-In Serial-Out (PISO), and Parallel-In Parallel-Out (PIPO). These are implemented by using Transmission Gate (TG)–based flip-flop structures in the GPDK 45 nm CMOS technology. Shift registers serve as critical sequential building blocks for data storage, buffering, and communication interfaces in digital systems. The primary work involves establishing optimized transistor-level schematics, analyzing their performance metrics (such as delay and power consumption), and verifying the physical design using industry-standard flows. The schematic-level designs utilized TG-based latches to achieve superior low-power and high-speed behavior. Post-implementation verification, including Design Rule Check (DRC) and Layout Versus Schematic (LVS), confirmed the fidelity of the physical design. The final results demonstrate that the TG based implementations in the 45 nm process achieve efficient operation with reduced leakage and improved switching characteristics, confirming their suitability for modern high-speed and low-power digital systems.
Copyright
Copyright © 2026 Donna Devaprasad, Mayavati Karalekar, Kanchika Kumta, Kavya Nagappa Vaddellappanavar, Deepak Sharma. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
