Paper Contents
Abstract
This paper presents an innovative circuit design for a Ternary Ripple Carry Adder (TRCA) utilizing a newly proposed Ternary 3:1 multiplexer (3:1 TMUX) and a proposed Ternary Half Adder (THA) and Ternary Full Adder (TFA). This study aims to attain minimal power consumption and propagation latency in the proposed circuits. The suggested Ternary Ripple Carry Adder circuit is evaluated against existing circuits and exhibits enhanced performance according to their performance parameters. Circuit analysis and simulations were performed with the Tanner EDA design environment at a 90 nm technology node. The simulation findings demonstrate that the suggested designs surpass other existing circuits regarding latency and power-delay product (PDP), making them appropriate for high-performance ternary computational circuits.
Copyright
Copyright © 2024 Rachakonda Arun Srivasthava, Bandi Srada. This is an open access article distributed under the Creative Commons Attribution License.
